Single Event Upset (SEU) is a radiation-induced error in a semiconductor device caused when charged particles lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs. The electron-hole pairs form a parasitic conduction path, which can cause a false transition on a node. The false transition, or glitch, can propagate through the semiconductor device and may ultimately result in the disturbance of a node containing state information, such as an output of a latch, register, or gate.
Typically, an SEU is caused by ionizing radiation components, such as neutrons, protons, and heavy ions. The ionizing radiation components are abundant in space and at commercial flight altitudes. Additionally, an SEU may be caused by alpha particles from the decay of trace concentrations of uranium and thorium present in some integrated circuit packaging. As another example, an SEU may be caused by detonating nuclear weapons. When a nuclear weapon is detonated, intense fluxes of gamma rays, x-rays, and other high energy particles are created, which may cause SEU.
Digital Single Event Transient (DSET) is a type of SEU that happens when a transient pulse occurs near a capturing clock edge of a register. Because of the close timing between the transient pulse and the clock pulse, the register may store an incorrect state. As registers are common in circuit designs, it is beneficial to harden registers against DSET so that the registers can be used in space and other harsh environments where SEU is a concern.
A common hardening technique is triple modular redundancy (TMR). TMR is implemented by creating three identical copies of a module and feeding the module outputs into a majority voter, which determines the most popular of the three outputs. Thus, if one of the three modules produces an incorrect result, the majority voter still provides the correct result as an output since the other two modules' outputs agree. Unfortunately, TMR does not completely protect against DSET unless implemented in both combinational logic and the register. If TMR is implemented only in the register, and not in the logic, transient glitches in the logic can still cause incorrect data to be stored in the TMR register. Another common hardening technique, adding a switchable RC delay that is switched into a low impedance or bypassed state when the latch is written, is also ineffective in protecting against DSET.
Typically, filtering is used to protect against DSET. However, filtering DSET pulses on a data path increases the setup time of the register, regardless of whether a DSET event is occurring. For example, Honeywell's HX5000 SET hardened register adds about ins of delay. The increased setup time is undesirable because it reduces the useful operating frequency of the register.
Thus, it would be beneficial to harden a register without filtering so that the register may be used in applications that are susceptible to DSET.